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authorClifford Wolf <clifford@clifford.at>2016-11-15 13:35:19 +0100
committerClifford Wolf <clifford@clifford.at>2016-11-15 13:35:19 +0100
commit70d7a02cae7ef38eb4f3afcf325979b80e87518e (patch)
tree431ec96bb8b4e8d4749cac8fd2bde537b070f354 /frontends/verilog/verilog_parser.y
parenta926a6afc2cf6ab7aed2c18950c6cd38d21f2a51 (diff)
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Added support for hierarchical defparams
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
-rw-r--r--frontends/verilog/verilog_parser.y5
1 files changed, 2 insertions, 3 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 5bbda5355..607c48a81 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -666,14 +666,13 @@ defparam_decl_list:
single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
single_defparam_decl:
- range hierarchical_id '=' expr {
+ range rvalue '=' expr {
AstNode *node = new AstNode(AST_DEFPARAM);
- node->str = *$2;
+ node->children.push_back($2);
node->children.push_back($4);
if ($1 != NULL)
node->children.push_back($1);
ast_stack.back()->children.push_back(node);
- delete $2;
};
wire_decl: