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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-04-30 13:19:27 -0700 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-04-30 13:19:27 -0700 |
| commit | 58650ffe876d1caedd8ffc9b0207f5cf75eef97b (patch) | |
| tree | 5389584f1c3ad8c9e9003e78d4b6e22dca5e3a83 /frontends/verilog/verilog_parser.y | |
| parent | 354ba5ba83f7b1fc3bb07aa6bf26dde7a00201d1 (diff) | |
| parent | e35fe1344dd4c8f11632ed2a7f5b0463352a1ee4 (diff) | |
| download | yosys-58650ffe876d1caedd8ffc9b0207f5cf75eef97b.tar.gz yosys-58650ffe876d1caedd8ffc9b0207f5cf75eef97b.tar.bz2 yosys-58650ffe876d1caedd8ffc9b0207f5cf75eef97b.zip | |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 52685f637..40968d17a 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -59,7 +59,7 @@ namespace VERILOG_FRONTEND { std::vector<char> case_type_stack; bool do_not_require_port_stubs; bool default_nettype_wire; - bool sv_mode, formal_mode, lib_mode; + bool sv_mode, formal_mode, noblackbox_mode, lib_mode, nowb_mode; bool noassert_mode, noassume_mode, norestrict_mode; bool assume_asserts_mode, assert_assumes_mode; bool current_wire_rand, current_wire_const; |