diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:45:49 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 11:45:49 -0700 |
| commit | 4486a98fd5928a4e3cdf9cd27c27b7dd821513bb (patch) | |
| tree | 0afd22de8a09ab3995355e3813015c4523bd63fd /frontends/verilog/verilog_parser.y | |
| parent | cbb85e40e87fbfb1602bb934ed76a97efb9e55c6 (diff) | |
| parent | ec88129a5cf510afc39ea12efa6059bed3eadfc3 (diff) | |
| download | yosys-4486a98fd5928a4e3cdf9cd27c27b7dd821513bb.tar.gz yosys-4486a98fd5928a4e3cdf9cd27c27b7dd821513bb.tar.bz2 yosys-4486a98fd5928a4e3cdf9cd27c27b7dd821513bb.zip | |
Merge remote-tracking branch 'origin/xc7srl' into xc7mux
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 52685f637..40968d17a 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -59,7 +59,7 @@ namespace VERILOG_FRONTEND { std::vector<char> case_type_stack; bool do_not_require_port_stubs; bool default_nettype_wire; - bool sv_mode, formal_mode, lib_mode; + bool sv_mode, formal_mode, noblackbox_mode, lib_mode, nowb_mode; bool noassert_mode, noassume_mode, norestrict_mode; bool assume_asserts_mode, assert_assumes_mode; bool current_wire_rand, current_wire_const; |