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| author | whitequark <whitequark@whitequark.org> | 2020-06-19 19:57:25 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-19 19:57:25 +0000 |
| commit | 338ecbe02f8bb3cc4d69de1445c7f398a814b4e4 (patch) | |
| tree | 20b447f4d8553aa589e90b133e23b2e4dee186b9 /frontends/verilog/verilog_parser.y | |
| parent | d5d0cc88d272b85c3be3677993596dcfa82d579f (diff) | |
| parent | 3ccdab940cd054d996a5ce94010918edd782cae0 (diff) | |
| download | yosys-338ecbe02f8bb3cc4d69de1445c7f398a814b4e4.tar.gz yosys-338ecbe02f8bb3cc4d69de1445c7f398a814b4e4.tar.bz2 yosys-338ecbe02f8bb3cc4d69de1445c7f398a814b4e4.zip | |
Merge pull request #2178 from boqwxp/design-select
rtlil: Add `Design::select()` for selecting whole modules
Diffstat (limited to 'frontends/verilog/verilog_parser.y')
0 files changed, 0 insertions, 0 deletions