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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-13 14:21:20 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-13 14:21:20 +0200 |
| commit | f13e3873212fb4338ee3dd180cb9b0cd3d134935 (patch) | |
| tree | f2cfe06b4332859abb143fe4ed69f054de491522 /frontends/verilog/verilog_lexer.l | |
| parent | 34f34be17c891ffb99ca76700634aeff9da76bde (diff) | |
| download | yosys-f13e3873212fb4338ee3dd180cb9b0cd3d134935.tar.gz yosys-f13e3873212fb4338ee3dd180cb9b0cd3d134935.tar.bz2 yosys-f13e3873212fb4338ee3dd180cb9b0cd3d134935.zip | |
SystemVerilog also has assume(), added implicit -D FORMAL
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
| -rw-r--r-- | frontends/verilog/verilog_lexer.l | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 47c1a0e63..69a8ddaad 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -170,7 +170,7 @@ YOSYS_NAMESPACE_END "always_latch" { SV_KEYWORD(TOK_ALWAYS); } "assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); } -"assume" { if (formal_mode) return TOK_ASSUME; return TOK_ID; } +"assume" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); } "property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); } "logic" { SV_KEYWORD(TOK_REG); } "bit" { SV_KEYWORD(TOK_REG); } |