Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

1 files changed, 15 insertions, 2 deletions

diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h
index 8b4fae6e9..af6495f8f 100644
--- a/frontends/verilog/verilog_frontend.h
+++ b/frontends/verilog/verilog_frontend.h
@@ -29,12 +29,14 @@
 #ifndef VERILOG_FRONTEND_H
 #define VERILOG_FRONTEND_H
 
-#include "kernel/rtlil.h"
+#include "kernel/yosys.h"
 #include "frontends/ast/ast.h"
 #include <stdio.h>
 #include <stdint.h>
 #include <list>
 
+YOSYS_NAMESPACE_BEGIN
+
 namespace VERILOG_FRONTEND
 {
 	// this variable is set to a new AST_DESIGN node and then filled with the AST by the bison parser
@@ -42,10 +44,21 @@ namespace VERILOG_FRONTEND
 
 	// this function converts a Verilog constant to an AST_CONSTANT node
 	AST::AstNode *const2ast(std::string code, char case_type = 0);
+
+	// state of `default_nettype
+	extern bool default_nettype_wire;
+
+	// running in SystemVerilog mode
+	extern bool sv_mode;
+
+	// lexer input stream
+	extern std::istream *lexin;
 }
 
 // the pre-processor
-std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::map<std::string, std::string> pre_defines_map, const std::list<std::string> include_dirs);
+std::string frontend_verilog_preproc(std::istream &f, std::string filename, const std::map<std::string, std::string> pre_defines_map, const std::list<std::string> include_dirs);
+
+YOSYS_NAMESPACE_END
 
 // the usual bison/flex stuff
 extern int frontend_verilog_yydebug;