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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-09 10:02:19 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-09 10:02:19 -0800 |
| commit | d979648b7af4eb5fab042ac55ff2fb40e0c17a89 (patch) | |
| tree | eba045916d3cd40d29b173ad0f731179e1bd2acf /frontends/verilog/verilog_frontend.cc | |
| parent | 943ea4bf9ea34960bfce517450a8a466d1c54ed3 (diff) | |
| download | yosys-d979648b7af4eb5fab042ac55ff2fb40e0c17a89.tar.gz yosys-d979648b7af4eb5fab042ac55ff2fb40e0c17a89.tar.bz2 yosys-d979648b7af4eb5fab042ac55ff2fb40e0c17a89.zip | |
read_aiger: more accurate debug message
Diffstat (limited to 'frontends/verilog/verilog_frontend.cc')
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