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author | Clifford Wolf <clifford@clifford.at> | 2015-10-13 14:21:20 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-10-13 14:21:20 +0200 |
commit | f13e3873212fb4338ee3dd180cb9b0cd3d134935 (patch) | |
tree | f2cfe06b4332859abb143fe4ed69f054de491522 /frontends/verilog/preproc.cc | |
parent | 34f34be17c891ffb99ca76700634aeff9da76bde (diff) | |
download | yosys-f13e3873212fb4338ee3dd180cb9b0cd3d134935.tar.gz yosys-f13e3873212fb4338ee3dd180cb9b0cd3d134935.tar.bz2 yosys-f13e3873212fb4338ee3dd180cb9b0cd3d134935.zip |
SystemVerilog also has assume(), added implicit -D FORMAL
Diffstat (limited to 'frontends/verilog/preproc.cc')
-rw-r--r-- | frontends/verilog/preproc.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index fb8a7b95f..997920b89 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -39,6 +39,7 @@ #include <string.h> YOSYS_NAMESPACE_BEGIN +using namespace VERILOG_FRONTEND; static std::list<std::string> output_code; static std::list<std::string> input_buffer; @@ -222,7 +223,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons input_file(f, filename); defines_map["YOSYS"] = "1"; - defines_map["SYNTHESIS"] = "1"; + defines_map[formal_mode ? "FORMAL" : "SYNTHESIS"] = "1"; while (!input_buffer.empty()) { |