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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-08 11:49:55 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-08 11:51:04 +0200 |
| commit | 27b5347a871d209ec4cba094e1203cc896c9c4b3 (patch) | |
| tree | 2639232409c190a864a965af72ac2f9d7a6b8d9e /frontends/verilog/preproc.cc | |
| parent | 72149aba2e8fece72450a81142a44d123154fd12 (diff) | |
| download | yosys-27b5347a871d209ec4cba094e1203cc896c9c4b3.tar.gz yosys-27b5347a871d209ec4cba094e1203cc896c9c4b3.tar.bz2 yosys-27b5347a871d209ec4cba094e1203cc896c9c4b3.zip | |
Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behavior
Diffstat (limited to 'frontends/verilog/preproc.cc')
0 files changed, 0 insertions, 0 deletions