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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-02 17:11:54 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-02 17:11:54 +0100 |
| commit | 1bd67d792eefeb7e72bf74f80776b0d5e41d771a (patch) | |
| tree | 06c383bbd0a50e25a57690dca5be4a9b57838687 /frontends/verilog/preproc.cc | |
| parent | 474831643c9e75bd3930f566bc746bb4e330bce9 (diff) | |
| download | yosys-1bd67d792eefeb7e72bf74f80776b0d5e41d771a.tar.gz yosys-1bd67d792eefeb7e72bf74f80776b0d5e41d771a.tar.bz2 yosys-1bd67d792eefeb7e72bf74f80776b0d5e41d771a.zip | |
Define YOSYS and SYNTHESIS in preproc
Diffstat (limited to 'frontends/verilog/preproc.cc')
| -rw-r--r-- | frontends/verilog/preproc.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index b4e77c31b..4e5d16599 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -221,7 +221,8 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons input_buffer_charp = 0; input_file(f, filename); - defines_map["__YOSYS__"] = "1"; + defines_map["YOSYS"] = "1"; + defines_map["SYNTHESIS"] = "1"; while (!input_buffer.empty()) { |