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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-12 20:09:47 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2019-03-12 20:09:47 +0100 |
| commit | ab5b50ae3c9e63fe3da3ae0451500c1cb5be1743 (patch) | |
| tree | 05799d46025b2486c4b6e51f8054b52d6f04fcfa /frontends/verilog/const2ast.cc | |
| parent | ef48b62cb1206a3b72c00735fe817683ccf0f005 (diff) | |
| download | yosys-ab5b50ae3c9e63fe3da3ae0451500c1cb5be1743.tar.gz yosys-ab5b50ae3c9e63fe3da3ae0451500c1cb5be1743.tar.bz2 yosys-ab5b50ae3c9e63fe3da3ae0451500c1cb5be1743.zip | |
Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verilog/const2ast.cc')
0 files changed, 0 insertions, 0 deletions