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| author | Benedikt Tutzer <e1225461@student.tuwien.ac.at> | 2019-04-30 13:22:33 +0200 |
|---|---|---|
| committer | Benedikt Tutzer <e1225461@student.tuwien.ac.at> | 2019-04-30 13:22:33 +0200 |
| commit | dc06e3a28bdb902d9b95d5d4ff2f163ee010aff4 (patch) | |
| tree | 8d6a4b7ebcf96a2fe5b5bdb21b821555a3a3b994 /frontends/verilog/Makefile.inc | |
| parent | 124a284487ce4c7b58f2377f04123e15e83e478d (diff) | |
| parent | 314ff1e4ca00ef8024bbb0d2f031efd78b01f9a1 (diff) | |
| download | yosys-dc06e3a28bdb902d9b95d5d4ff2f163ee010aff4.tar.gz yosys-dc06e3a28bdb902d9b95d5d4ff2f163ee010aff4.tar.bz2 yosys-dc06e3a28bdb902d9b95d5d4ff2f163ee010aff4.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python_bindings
Diffstat (limited to 'frontends/verilog/Makefile.inc')
| -rw-r--r-- | frontends/verilog/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc index dbaace585..0a1f97ac0 100644 --- a/frontends/verilog/Makefile.inc +++ b/frontends/verilog/Makefile.inc @@ -14,6 +14,8 @@ frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l $(Q) mkdir -p $(dir $@) $(P) flex -o frontends/verilog/verilog_lexer.cc $< +frontends/verilog/verilog_parser.tab.o: CXXFLAGS += -DYYMAXDEPTH=100000 + OBJS += frontends/verilog/verilog_parser.tab.o OBJS += frontends/verilog/verilog_lexer.o OBJS += frontends/verilog/preproc.o |