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| author | David Shah <dave@ds0.me> | 2019-09-20 11:46:37 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-10-03 09:54:14 +0100 |
| commit | af25585170f87506bcc7dbe5afe0fec868290d5b (patch) | |
| tree | b66b8b2c1d4bd322d6179b9acc111d512f3354da /frontends/verilog/Makefile.inc | |
| parent | 30d23260309ef392a0e69fe5294c38b71ad0692e (diff) | |
| download | yosys-af25585170f87506bcc7dbe5afe0fec868290d5b.tar.gz yosys-af25585170f87506bcc7dbe5afe0fec868290d5b.tar.bz2 yosys-af25585170f87506bcc7dbe5afe0fec868290d5b.zip | |
sv: Add support for memories of a typedef
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'frontends/verilog/Makefile.inc')
0 files changed, 0 insertions, 0 deletions