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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-04 13:37:58 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-04 13:37:58 +0100 |
| commit | abf81d76835d3ebb372ea128ee15cf6fb2c8f03a (patch) | |
| tree | b2b8ca6f4050adb4b12109a098fb6f7cee81aecf /frontends/verilog/Makefile.inc | |
| parent | 51cfcd8331bb06b1fea3ec62a48fcbb092e7df70 (diff) | |
| download | yosys-abf81d76835d3ebb372ea128ee15cf6fb2c8f03a.tar.gz yosys-abf81d76835d3ebb372ea128ee15cf6fb2c8f03a.tar.bz2 yosys-abf81d76835d3ebb372ea128ee15cf6fb2c8f03a.zip | |
Added some missing .gitignore in manual/
Diffstat (limited to 'frontends/verilog/Makefile.inc')
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