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| author | whitequark <whitequark@whitequark.org> | 2020-06-19 06:15:33 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-19 06:15:33 +0000 |
| commit | ede4b10da8fdbdcff900b93c6c723516901483ff (patch) | |
| tree | d949c995f56d6c07dfe7d18ca46547a3296079b6 /frontends/verific | |
| parent | bcbd44c673e07c44da735ef1d7f6eb2b6c328f98 (diff) | |
| parent | 60478a8e3a7b929ea7e4f4cd1b538b41ca1f34bb (diff) | |
| download | yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.gz yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.tar.bz2 yosys-ede4b10da8fdbdcff900b93c6c723516901483ff.zip | |
Merge pull request #2173 from whitequark/use-cxx11-final-override
Use C++11 final/override/[[noreturn]]
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/verific.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index a22a8a93d..1630c57bc 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2008,7 +2008,7 @@ bool check_noverific_env() struct VerificPass : public Pass { VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -2147,7 +2147,7 @@ struct VerificPass : public Pass { log("\n"); } #ifdef YOSYS_ENABLE_VERIFIC - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { static bool set_verific_global_flags = true; @@ -2582,7 +2582,7 @@ struct VerificPass : public Pass { } #else /* YOSYS_ENABLE_VERIFIC */ - void execute(std::vector<std::string>, RTLIL::Design *) YS_OVERRIDE { + void execute(std::vector<std::string>, RTLIL::Design *) override { log_cmd_error("This version of Yosys is built without Verific support.\n" "\n" "Use Symbiotic EDA Suite if you need Yosys+Verifc.\n" @@ -2596,7 +2596,7 @@ struct VerificPass : public Pass { struct ReadPass : public Pass { ReadPass() : Pass("read", "load HDL designs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -2637,7 +2637,7 @@ struct ReadPass : public Pass { log("Verific support. The default is to use Verific if it is available.\n"); log("\n"); } - void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector<std::string> args, RTLIL::Design *design) override { #ifdef YOSYS_ENABLE_VERIFIC static bool verific_available = !check_noverific_env(); |