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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-12 15:21:06 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-12 15:21:06 +0200 |
| commit | 593264e9edce8b1df1d5b691353fa592261d4f3b (patch) | |
| tree | d823596064cab0dff9971cd44525a13fd8fbf40e /frontends/verific | |
| parent | cad98bcd89cd9747f3ea9e35eed8d9bbedd64d7a (diff) | |
| download | yosys-593264e9edce8b1df1d5b691353fa592261d4f3b.tar.gz yosys-593264e9edce8b1df1d5b691353fa592261d4f3b.tar.bz2 yosys-593264e9edce8b1df1d5b691353fa592261d4f3b.zip | |
Fixed building verific bindings
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/build_amd64.txt | 2 | ||||
| -rw-r--r-- | frontends/verific/verific.cc | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/frontends/verific/build_amd64.txt b/frontends/verific/build_amd64.txt index 2f325e515..2c3ba7b4d 100644 --- a/frontends/verific/build_amd64.txt +++ b/frontends/verific/build_amd64.txt @@ -6,7 +6,7 @@ only have the i386 eval version of Verific: 1.) Use a Makefile.conf like the following one: --snip-- -CONFIG := clang-debug +CONFIG := clang ENABLE_TCL := 0 ENABLE_QT4 := 0 ENABLE_ABC := 0 diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 30f452181..1ffcc4229 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -687,7 +687,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist* RTLIL::SigSpec data = operatorOutput(inst, net_map, module); RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), "$memrd"); - cell->parameters["\\MEMID"] = memory->name; + cell->parameters["\\MEMID"] = memory->name.str(); cell->parameters["\\CLK_ENABLE"] = false; cell->parameters["\\CLK_POLARITY"] = true; cell->parameters["\\TRANSPARENT"] = false; @@ -709,7 +709,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist* RTLIL::SigSpec data = operatorInput2(inst, net_map); RTLIL::Cell *cell = module->addCell(RTLIL::escape_id(inst->Name()), "$memwr"); - cell->parameters["\\MEMID"] = memory->name; + cell->parameters["\\MEMID"] = memory->name.str(); cell->parameters["\\CLK_ENABLE"] = false; cell->parameters["\\CLK_POLARITY"] = true; cell->parameters["\\PRIORITY"] = 0; |