diff options
| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-12-03 09:49:05 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-12-03 09:49:05 +0100 |
| commit | 3ebfa3fb84b707bf963973736fb940f32b74304c (patch) | |
| tree | 7576fe4f6dd3bd6bb37d735de85d4c084cb01965 /frontends/verific | |
| parent | 2be110cb0ba645f95f62ee01b6a6fa46a85d5b26 (diff) | |
| download | yosys-3ebfa3fb84b707bf963973736fb940f32b74304c.tar.gz yosys-3ebfa3fb84b707bf963973736fb940f32b74304c.tar.bz2 yosys-3ebfa3fb84b707bf963973736fb940f32b74304c.zip | |
Make sure cell names are unique for wide operators
Diffstat (limited to 'frontends/verific')
| -rw-r--r-- | frontends/verific/verific.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 47020f105..dccdcb482 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -896,7 +896,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr for (offset = 0; offset < GetSize(sig_acond); offset += width) { for (width = 1; offset+width < GetSize(sig_acond); width++) if (sig_acond[offset] != sig_acond[offset+width]) break; - cell = clocking.addAldff(inst_name, sig_acond[offset], sig_adata.extract(offset, width), + cell = clocking.addAldff(module->uniquify(inst_name), sig_acond[offset], sig_adata.extract(offset, width), sig_d.extract(offset, width), sig_q.extract(offset, width)); import_attributes(cell->attributes, inst); } @@ -922,7 +922,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr if (sig_acond[offset] != sig_acond[offset+width]) break; RTLIL::SigSpec sig_set = module->Mux(NEW_ID, RTLIL::SigSpec(0, width), sig_adata.extract(offset, width), sig_acond[offset]); RTLIL::SigSpec sig_clr = module->Mux(NEW_ID, RTLIL::SigSpec(0, width), module->Not(NEW_ID, sig_adata.extract(offset, width)), sig_acond[offset]); - cell = module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), sig_set, sig_clr, + cell = module->addDlatchsr(module->uniquify(inst_name), net_map_at(inst->GetControl()), sig_set, sig_clr, sig_d.extract(offset, width), sig_q.extract(offset, width)); import_attributes(cell->attributes, inst); } |