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| author | Jannis Harder <me@jix.one> | 2022-05-09 16:07:39 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-09 16:07:39 +0200 |
| commit | 5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd (patch) | |
| tree | fa7a31d02a6de07779a4f7b7934fb662c5efc06d /frontends/verific/verific.cc | |
| parent | d562bfd165b3c107abf717d2661c44aa2b7740fb (diff) | |
| parent | 96f64f4788ca64adde55421a6abadefd182d9a1a (diff) | |
| download | yosys-5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd.tar.gz yosys-5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd.tar.bz2 yosys-5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd.zip | |
Merge pull request #3297 from jix/sva_nested_clk_else
verific: Fix conditions of SVAs with explicit clocks within procedures
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index d19d837ff..4eb66851d 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1873,15 +1873,19 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a if (inst_mux == nullptr || inst_mux->Type() != PRIM_MUX) break; - if (!inst_mux->GetInput1()->IsPwr()) + bool pwr1 = inst_mux->GetInput1()->IsPwr(); + bool pwr2 = inst_mux->GetInput2()->IsPwr(); + + if (!pwr1 && !pwr2) break; - Net *sva_net = inst_mux->GetInput2(); + Net *sva_net = pwr1 ? inst_mux->GetInput2() : inst_mux->GetInput1(); if (!verific_is_sva_net(importer, sva_net)) break; body_net = sva_net; cond_net = inst_mux->GetControl(); + cond_pol = pwr1; } while (0); clock_net = net; |