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| author | tklam <tklam@easylogic.hk> | 2018-10-13 22:52:31 +0800 |
|---|---|---|
| committer | tklam <tklam@easylogic.hk> | 2018-10-13 22:52:31 +0800 |
| commit | 3c5406c31b416bccb5cc98398b7e5a77d017a138 (patch) | |
| tree | 2b8eb6a60b3ac75cdb7354d9a0c00f77a5577555 /frontends/verific/verific.cc | |
| parent | 27c46d94e32a45762b3a424d6c7bfcd3ce7a1b12 (diff) | |
| parent | 9850de405a11fe93e4562c86be0a0830b83c2785 (diff) | |
| download | yosys-3c5406c31b416bccb5cc98398b7e5a77d017a138.tar.gz yosys-3c5406c31b416bccb5cc98398b7e5a77d017a138.tar.bz2 yosys-3c5406c31b416bccb5cc98398b7e5a77d017a138.zip | |
Merge branch 'master' of https://github.com/YosysHQ/yosys
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index c5fa58313..dba3b0f0c 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -118,6 +118,18 @@ RTLIL::SigBit VerificImporter::net_map_at(Net *net) return net_map.at(net); } +bool is_blackbox(Netlist *nl) +{ + if (nl->IsBlackBox()) + return true; + + const char *attr = nl->GetAttValue("blackbox"); + if (attr != nullptr && strcmp(attr, "0")) + return true; + + return false; +} + void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj) { MapIter mi; @@ -709,7 +721,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se netlist = nl; if (design->has(module_name)) { - if (!nl->IsOperator()) + if (!nl->IsOperator() && !is_blackbox(nl)) log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name()); return; } @@ -718,7 +730,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se module->name = module_name; design->add(module); - if (nl->IsBlackBox()) { + if (is_blackbox(nl)) { log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name)); module->set_bool_attribute("\\blackbox"); } else { @@ -1676,6 +1688,7 @@ YOSYS_NAMESPACE_END PRIVATE_NAMESPACE_BEGIN +#ifdef YOSYS_ENABLE_VERIFIC bool check_noverific_env() { const char *e = getenv("YOSYS_NOVERIFIC"); @@ -1685,6 +1698,7 @@ bool check_noverific_env() return false; return true; } +#endif struct VerificPass : public Pass { VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { } |