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| author | Clifford Wolf <clifford@clifford.at> | 2018-05-25 15:41:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-05-25 15:41:45 +0200 |
| commit | 001c9f1d45749535452d082a7c92a17954b603b8 (patch) | |
| tree | f2563fa5e64499913800699825af4b66d1573e66 /frontends/verific/verific.cc | |
| parent | 251562a4918576bd485bcdcc908c0ac780689a77 (diff) | |
| download | yosys-001c9f1d45749535452d082a7c92a17954b603b8.tar.gz yosys-001c9f1d45749535452d082a7c92a17954b603b8.tar.bz2 yosys-001c9f1d45749535452d082a7c92a17954b603b8.zip | |
Fix Verific handling of single-bit anyseq/anyconst wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 19273c69a..60fa6db3b 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -244,7 +244,9 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr } if (inst->Type() == PRIM_BUF) { - module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput())); + auto outnet = inst->GetOutput(); + if (!any_all_nets.count(outnet)) + module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(outnet)); return true; } @@ -1074,7 +1076,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (inst->Type() == PRIM_BUF) { auto outnet = inst->GetOutput(); - if (!anyconst_nets.count(outnet) && !anyseq_nets.count(outnet) && !allconst_nets.count(outnet) && !allseq_nets.count(outnet)) + if (!any_all_nets.count(outnet)) module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(outnet)); continue; } |