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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-31 13:30:52 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-31 13:30:52 +0200 |
| commit | acd8bc0a7496c69864a7dd032eb7f4db7e2e1f2d (patch) | |
| tree | 2c46c9aa421b765ab4ae9d93e1121d481297fa48 /frontends/verific/Makefile.inc | |
| parent | b4f38cca77a78884ce215190935af78cae92c4db (diff) | |
| parent | 5be5bd0fb61a9c8d1efa7e8c233ea0100cc32641 (diff) | |
| download | yosys-acd8bc0a7496c69864a7dd032eb7f4db7e2e1f2d.tar.gz yosys-acd8bc0a7496c69864a7dd032eb7f4db7e2e1f2d.tar.bz2 yosys-acd8bc0a7496c69864a7dd032eb7f4db7e2e1f2d.zip | |
Merge pull request #1233 from YosysHQ/clifford/defer
Call "read_verilog" with -defer from "read"
Diffstat (limited to 'frontends/verific/Makefile.inc')
0 files changed, 0 insertions, 0 deletions