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authorEddie Hung <eddie@fpgeh.com>2019-11-22 15:13:18 -0800
committerEddie Hung <eddie@fpgeh.com>2019-11-22 15:13:18 -0800
commit2a54fa41c40969841ba0574ba725caa436b0212f (patch)
tree1dbf518fc73dbe253612bdb5e466c50b78bce44b /frontends/blif/blifparse.cc
parent6b9f90de789b1d0daf93ac1d2b608b057e7ca272 (diff)
parentc03b6a3e9cab9fc05b2d5b256676f5ddc6c2d763 (diff)
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Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'frontends/blif/blifparse.cc')
-rw-r--r--frontends/blif/blifparse.cc8
1 files changed, 7 insertions, 1 deletions
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index d17cacf29..cab210605 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -174,6 +174,12 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (module == nullptr)
goto error;
+ if (!strcmp(cmd, ".blackbox"))
+ {
+ module->attributes["\\blackbox"] = RTLIL::Const(1);
+ continue;
+ }
+
if (!strcmp(cmd, ".end"))
{
for (auto &wp : wideports_cache)
@@ -280,7 +286,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
goto error_with_reason;
}
- module->rename(lastcell, p);
+ module->rename(lastcell, RTLIL::escape_id(p));
continue;
}