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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 11:32:10 -0700 | 
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 11:32:10 -0700 | 
| commit | f890cfb63b71ae7b09e19c290ec70c358dcbe9cd (patch) | |
| tree | ea7602c378e794b5e7448361ba2a41d2d6a49c13 /frontends/ast | |
| parent | ab1d63a56595f11e10a5326bd83ce84d08badabe (diff) | |
| parent | 78b30bbb1102047585d1a2eac89b1c7f5ca7344e (diff) | |
| download | yosys-f890cfb63b71ae7b09e19c290ec70c358dcbe9cd.tar.gz yosys-f890cfb63b71ae7b09e19c290ec70c358dcbe9cd.tar.bz2 yosys-f890cfb63b71ae7b09e19c290ec70c358dcbe9cd.zip  | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/ast.cc | 18 | ||||
| -rw-r--r-- | frontends/ast/genrtlil.cc | 2 | ||||
| -rw-r--r-- | frontends/ast/simplify.cc | 8 | 
3 files changed, 14 insertions, 14 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 943466ee3..07ef0a86e 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -283,8 +283,8 @@ void AstNode::dumpAst(FILE *f, std::string indent) const  	if (!bits.empty()) {  		fprintf(f, " bits='");  		for (size_t i = bits.size(); i > 0; i--) -			fprintf(f, "%c", bits[i-1] == RTLIL::S0 ? '0' : -					bits[i-1] == RTLIL::S1 ? '1' : +			fprintf(f, "%c", bits[i-1] == State::S0 ? '0' : +					bits[i-1] == State::S1 ? '1' :  					bits[i-1] == RTLIL::Sx ? 'x' :  					bits[i-1] == RTLIL::Sz ? 'z' : '?');  		fprintf(f, "'(%d)", GetSize(bits)); @@ -716,7 +716,7 @@ AstNode *AstNode::mkconst_int(uint32_t v, bool is_signed, int width)  	node->integer = v;  	node->is_signed = is_signed;  	for (int i = 0; i < width; i++) { -		node->bits.push_back((v & 1) ? RTLIL::S1 : RTLIL::S0); +		node->bits.push_back((v & 1) ? State::S1 : State::S0);  		v = v >> 1;  	}  	node->range_valid = true; @@ -733,9 +733,9 @@ AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signe  	node->bits = v;  	for (size_t i = 0; i < 32; i++) {  		if (i < node->bits.size()) -			node->integer |= (node->bits[i] == RTLIL::S1) << i; +			node->integer |= (node->bits[i] == State::S1) << i;  		else if (is_signed && !node->bits.empty()) -			node->integer |= (node->bits.back() == RTLIL::S1) << i; +			node->integer |= (node->bits.back() == State::S1) << i;  	}  	node->range_valid = true;  	node->range_left = node->bits.size()-1; @@ -767,7 +767,7 @@ AstNode *AstNode::mkconst_str(const std::string &str)  	for (size_t i = 0; i < str.size(); i++) {  		unsigned char ch = str[str.size() - i - 1];  		for (int j = 0; j < 8; j++) { -			data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0); +			data.push_back((ch & 1) ? State::S1 : State::S0);  			ch = ch >> 1;  		}  	} @@ -780,7 +780,7 @@ AstNode *AstNode::mkconst_str(const std::string &str)  bool AstNode::bits_only_01() const  {  	for (auto bit : bits) -		if (bit != RTLIL::S0 && bit != RTLIL::S1) +		if (bit != State::S0 && bit != State::S1)  			return false;  	return true;  } @@ -1164,7 +1164,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump  				}  			} -			if (flag_icells && (*it)->str.substr(0, 2) == "\\$") +			if (flag_icells && (*it)->str.compare(0, 2, "\\$") == 0)  				(*it)->str = (*it)->str.substr(1);  			if (defer) @@ -1463,7 +1463,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString  {  	std::string stripped_name = name.str(); -	if (stripped_name.substr(0, 9) == "$abstract") +	if (stripped_name.compare(0, 9, "$abstract") == 0)  		stripped_name = stripped_name.substr(9);  	log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str()); diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 571ddd988..407a34472 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1516,7 +1516,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)  				AstNode *child = *it;  				if (child->type == AST_CELLTYPE) {  					cell->type = child->str; -					if (flag_icells && cell->type.substr(0, 2) == "\\$") +					if (flag_icells && cell->type.begins_with("\\$"))  						cell->type = cell->type.substr(1);  					continue;  				} diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 6fb94d80b..54b9efaad 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2319,7 +2319,7 @@ skip_dynamic_range_lvalue_expansion:;  				if (attr.first.str().rfind("\\via_celltype_defparam_", 0) == 0)  				{  					AstNode *cell_arg = new AstNode(AST_PARASET, attr.second->clone()); -					cell_arg->str = RTLIL::escape_id(attr.first.str().substr(strlen("\\via_celltype_defparam_"))); +					cell_arg->str = RTLIL::escape_id(attr.first.substr(strlen("\\via_celltype_defparam_")));  					cell->children.push_back(cell_arg);  				} @@ -2793,13 +2793,13 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m  		std::getline(f, line);  		for (int i = 0; i < GetSize(line); i++) { -			if (in_comment && line.substr(i, 2) == "*/") { +			if (in_comment && line.compare(i, 2, "*/") == 0) {  				line[i] = ' ';  				line[i+1] = ' ';  				in_comment = false;  				continue;  			} -			if (!in_comment && line.substr(i, 2) == "/*") +			if (!in_comment && line.compare(i, 2, "/*") == 0)  				in_comment = true;  			if (in_comment)  				line[i] = ' '; @@ -2808,7 +2808,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m  		while (1)  		{  			token = next_token(line, " \t\r\n"); -			if (token.empty() || token.substr(0, 2) == "//") +			if (token.empty() || token.compare(0, 2, "//") == 0)  				break;  			if (token[0] == '@') {  | 
