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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 19:57:42 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 19:57:42 +0100 |
| commit | 7d9a90396d119375567b42eb0ff4bb120c355d9a (patch) | |
| tree | 288b3027be14d0e2d42d394a86a57aaa45d65b67 /frontends/ast | |
| parent | 20175afd298be717aa91a96c9d8654859cf2dd2d (diff) | |
| download | yosys-7d9a90396d119375567b42eb0ff4bb120c355d9a.tar.gz yosys-7d9a90396d119375567b42eb0ff4bb120c355d9a.tar.bz2 yosys-7d9a90396d119375567b42eb0ff4bb120c355d9a.zip | |
Added verilog frontend -ignore_redef option
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/ast.cc | 11 | ||||
| -rw-r--r-- | frontends/ast/ast.h | 2 |
2 files changed, 9 insertions, 4 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index ffbcf314e..9054f78ce 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -763,7 +763,7 @@ static AstModule* process_module(AstNode *ast) } // create AstModule instances for all modules in the AST tree and add them to 'design' -void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt) +void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool ignore_redef) { current_ast = ast; flag_dump_ast1 = dump_ast1; @@ -777,9 +777,14 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump assert(current_ast->type == AST_DESIGN); for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) { - if (design->modules.count((*it)->str) != 0) - log_error("Re-definition of module `%s' at %s:%d!\n", + if (design->modules.count((*it)->str) != 0) { + if (!ignore_redef) + log_error("Re-definition of module `%s' at %s:%d!\n", + (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); + log_error("Ignoring re-definition of module `%s' at %s:%d!\n", (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); + continue; + } design->modules[(*it)->str] = process_module(*it); } } diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 349832256..fccabbe63 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -219,7 +219,7 @@ namespace AST }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code - void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false); + void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false, bool ignore_redef = false); // parametric modules are supported directly by the AST library // therfore we need our own derivate of RTLIL::Module with overloaded virtual functions |