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| author | whitequark <whitequark@whitequark.org> | 2020-06-04 11:23:06 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-04 11:23:06 +0000 |
| commit | 3bffd09d6423b70ca154527c363985ff048f807d (patch) | |
| tree | 5d38c0618e478722d8dcd0fb681ef443869f0b8c /frontends/ast | |
| parent | 44f1e651558c5063b6e0c4496d916abc23329751 (diff) | |
| parent | adb483ddfd3163a4efa08e09a35dd926377aa71d (diff) | |
| download | yosys-3bffd09d6423b70ca154527c363985ff048f807d.tar.gz yosys-3bffd09d6423b70ca154527c363985ff048f807d.tar.bz2 yosys-3bffd09d6423b70ca154527c363985ff048f807d.zip | |
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
Preserve 'signed'-ness of a verilog wire through RTLIL
Diffstat (limited to 'frontends/ast')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index cdc3adc9c..78e6fe5e0 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1065,6 +1065,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) wire->port_input = is_input; wire->port_output = is_output; wire->upto = range_swapped; + wire->is_signed = is_signed; for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) |