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| author | Clifford Wolf <clifford@clifford.at> | 2014-06-16 15:05:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-06-16 15:05:37 +0200 |
| commit | 82bbd2f0772e62555eb669eb64883d75de4ca29a (patch) | |
| tree | fb974ae6cf552f19ee6fe1cbf563373de5c4fb95 /frontends/ast/simplify.cc | |
| parent | 0c4c79c4c6f8a433ef4b141b1523bccc261f8231 (diff) | |
| download | yosys-82bbd2f0772e62555eb669eb64883d75de4ca29a.tar.gz yosys-82bbd2f0772e62555eb669eb64883d75de4ca29a.tar.bz2 yosys-82bbd2f0772e62555eb669eb64883d75de4ca29a.zip | |
Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012
Diffstat (limited to 'frontends/ast/simplify.cc')
| -rw-r--r-- | frontends/ast/simplify.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 80fd28d55..3f712510b 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1625,6 +1625,15 @@ skip_dynamic_range_lvalue_expansion:; if (a.bits[i] != b.bits[i]) a.bits[i] = RTLIL::State::Sx; newNode = mkconst_bits(a.bits, sign_hint); + } else if (children[1]->isConst() && children[2]->isConst()) { + newNode = new AstNode(AST_REALVALUE); + if (children[1]->asReal(sign_hint) == children[2]->asReal(sign_hint)) + newNode->realvalue = children[1]->asReal(sign_hint); + else + // IEEE Std 1800-2012 Sec. 11.4.11 states that the entry in Table 7-1 for + // the data type in question should be returned if the ?: is ambiguous. The + // value in Table 7-1 for the 'real' type is 0.0. + newNode->realvalue = 0.0; } } break; |