aboutsummaryrefslogtreecommitdiffstats
path: root/frontends/ast/genrtlil.cc
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2019-05-03 15:29:44 +0200
committerGitHub <noreply@github.com>2019-05-03 15:29:44 +0200
commit71ede7cb05ae35c90eccb80ffc413b4559ba7e60 (patch)
tree73229c3e02655a9fd3c9f2bb987f44b226d65fc7 /frontends/ast/genrtlil.cc
parent97423caddaafa0fbaca6f541a9c3e17f036b198b (diff)
parent6bbe2fdbf32e6335cdbecc21547e54992c3a606d (diff)
downloadyosys-71ede7cb05ae35c90eccb80ffc413b4559ba7e60.tar.gz
yosys-71ede7cb05ae35c90eccb80ffc413b4559ba7e60.tar.bz2
yosys-71ede7cb05ae35c90eccb80ffc413b4559ba7e60.zip
Merge pull request #976 from YosysHQ/clifford/fix974
Fix width detection of memory access with bit slice
Diffstat (limited to 'frontends/ast/genrtlil.cc')
-rw-r--r--frontends/ast/genrtlil.cc2
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index b3a2a84be..d4515babf 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -645,6 +645,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
if (!id_ast->children[0]->range_valid)
log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
+ if (children.size() > 1)
+ range = children[1];
} else
log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str());
if (range) {