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authorPepijn de Vos <pepijndevos@gmail.com>2019-10-21 10:51:34 +0200
committerPepijn de Vos <pepijndevos@gmail.com>2019-10-21 10:51:34 +0200
commit69fb3b8db21c8a50fa333bff3ef844af42729e0d (patch)
tree1a62aebe9ece22b19b4087f2c5cb5581b571c270 /frontends/ast/genrtlil.cc
parent72323e11a4ee222c0ce928669d33333c46fb25aa (diff)
parentfa989e59e5a37d804d8a82050e022b8f4b7070d8 (diff)
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Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
Diffstat (limited to 'frontends/ast/genrtlil.cc')
-rw-r--r--frontends/ast/genrtlil.cc1
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 407a34472..94f5c0a04 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -863,6 +863,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_PACKAGE:
case AST_MODPORT:
case AST_MODPORTMEMBER:
+ case AST_TYPEDEF:
break;
case AST_INTERFACEPORT: {
// If a port in a module with unknown type is found, mark it with the attribute 'is_interface'