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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-28 19:38:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-28 19:38:30 +0200 |
| commit | 48822e79a34880c5f0b07e9889e463e7b6d7111b (patch) | |
| tree | 801926693e8c9e4fe25a4ed570ad386e2da09fc6 /frontends/ast/genrtlil.cc | |
| parent | ec589659674ba9699b5dc73129ad69f25738e87e (diff) | |
| download | yosys-48822e79a34880c5f0b07e9889e463e7b6d7111b.tar.gz yosys-48822e79a34880c5f0b07e9889e463e7b6d7111b.tar.bz2 yosys-48822e79a34880c5f0b07e9889e463e7b6d7111b.zip | |
Removed left over debug code
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 9b8e0faa4..cb666679b 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -917,7 +917,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) children[0]->children[1]->clone() : children[0]->children[0]->clone()); fake_ast->children[0]->delete_children(); RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL(); - log_dump(width, shift_val, id2ast->range_swapped, source_width, id2ast->range_left, id2ast->range_right); if (id2ast->range_right != 0) shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right); if (id2ast->range_swapped) |