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author | Rupert Swarbrick <rswarbrick@gmail.com> | 2021-10-19 18:43:30 -0600 |
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committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-10-25 18:25:50 -0700 |
commit | bd16d01c0eed5c96a241e6ee9e56b8f7890319a1 (patch) | |
tree | b55271d7943d0a2482a3a3cbc708ed30bc8d5af2 /frontends/ast/ast.h | |
parent | ee230f2bb9a2fe473b0ddb6bcfa30a15b0f07c88 (diff) | |
download | yosys-bd16d01c0eed5c96a241e6ee9e56b8f7890319a1.tar.gz yosys-bd16d01c0eed5c96a241e6ee9e56b8f7890319a1.tar.bz2 yosys-bd16d01c0eed5c96a241e6ee9e56b8f7890319a1.zip |
Split out logic for reprocessing an AstModule
This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
Diffstat (limited to 'frontends/ast/ast.h')
-rw-r--r-- | frontends/ast/ast.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 63104bca4..66bbdd7b4 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -348,7 +348,7 @@ namespace AST RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, bool mayfail) override; RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail) override; std::string derive_common(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> ¶meters, AstNode **new_ast_out, bool quiet = false); - void reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override; + void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces) override; RTLIL::Module *clone() const override; void loadconfig() const; }; @@ -395,6 +395,18 @@ namespace AST_INTERNAL extern dict<std::string, pool<int>> current_memwr_visible; struct LookaheadRewriter; struct ProcessGenerator; + + // Create and add a new AstModule from new_ast, then use it to replace + // old_module in design, renaming old_module to move it out of the way. + // Return the new module. + // + // If original_ast is not null, it will be used as the AST node for the + // new module. Otherwise, new_ast will be used. + RTLIL::Module * + process_and_replace_module(RTLIL::Design *design, + RTLIL::Module *old_module, + AST::AstNode *new_ast, + AST::AstNode *original_ast = nullptr); } YOSYS_NAMESPACE_END |