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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:17:21 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:17:21 +0100 |
| commit | 609caa23b5e12547c043dc4a1827d1a531af1992 (patch) | |
| tree | 297e7d5b77b28eebccc3bd8e7af318f174165744 /frontends/ast/ast.h | |
| parent | 1e6836933d8b74d391f816ccdcf71c972f8b1db1 (diff) | |
| download | yosys-609caa23b5e12547c043dc4a1827d1a531af1992.tar.gz yosys-609caa23b5e12547c043dc4a1827d1a531af1992.tar.bz2 yosys-609caa23b5e12547c043dc4a1827d1a531af1992.zip | |
Implemented correct handling of signed module parameters
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index de32a2bb9..f9f47f6a4 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -227,7 +227,7 @@ namespace AST AstNode *ast; bool nolatches, nomem2reg, mem2reg, lib, noopt; virtual ~AstModule(); - virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters); + virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters, std::set<RTLIL::IdString> signed_parameters); virtual void update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes); virtual RTLIL::Module *clone() const; }; |