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| author | Clifford Wolf <clifford@clifford.at> | 2013-12-04 21:06:54 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-12-04 21:06:54 +0100 |
| commit | 4a4a3fc3377243d85100b829a0f6b785376cce9f (patch) | |
| tree | 689dda333df9ac7012ce460e8f7e801b631c0882 /frontends/ast/ast.h | |
| parent | f4b46ed31e5f5c41bbd4ee1fdf996ecdc2010174 (diff) | |
| download | yosys-4a4a3fc3377243d85100b829a0f6b785376cce9f.tar.gz yosys-4a4a3fc3377243d85100b829a0f6b785376cce9f.tar.bz2 yosys-4a4a3fc3377243d85100b829a0f6b785376cce9f.zip | |
Various improvements in support for generate statements
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index f90fe9b7b..ab1b9bec5 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -116,6 +116,7 @@ namespace AST AST_GENVAR, AST_GENFOR, AST_GENIF, + AST_GENCASE, AST_GENBLOCK, AST_POSEDGE, @@ -218,6 +219,7 @@ namespace AST RTLIL::Const bitsAsConst(int width = -1); RTLIL::Const asAttrConst(); RTLIL::Const asParaConst(); + bool asBool(); }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code |