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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-22 13:10:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-22 13:10:42 -0700 |
| commit | 46753cf89fd132d2ca8688053f4cf7247671d241 (patch) | |
| tree | 53b082685d006e6aa4a51abcb419eb9df5f11fde /frontends/ast/ast.h | |
| parent | 4cc6b3e942a54e94f472df7817788dc321955a20 (diff) | |
| parent | a440f82586eda461ae2a90cba7a14d7078c41f37 (diff) | |
| download | yosys-46753cf89fd132d2ca8688053f4cf7247671d241.tar.gz yosys-46753cf89fd132d2ca8688053f4cf7247671d241.tar.bz2 yosys-46753cf89fd132d2ca8688053f4cf7247671d241.zip | |
Merge remote-tracking branch 'origin/master' into xc7srl
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 8b185ff51..ddd59d4be 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -282,7 +282,7 @@ namespace AST }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code - void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, + void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); // parametric modules are supported directly by the AST library |