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| author | Clifford Wolf <clifford@clifford.at> | 2013-08-19 19:49:14 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-08-19 19:49:14 +0200 |
| commit | 4214561890c4d25d8a172ea7d8b8201f800b3c90 (patch) | |
| tree | ac56708adda22debe4714e9017339157ee77a9d7 /frontends/ast/ast.h | |
| parent | a860efa8ac37dfe20cd74324dd02136082aa2c1c (diff) | |
| download | yosys-4214561890c4d25d8a172ea7d8b8201f800b3c90.tar.gz yosys-4214561890c4d25d8a172ea7d8b8201f800b3c90.tar.bz2 yosys-4214561890c4d25d8a172ea7d8b8201f800b3c90.zip | |
Improved ast dumping (ast/verilog frontend)
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index f6bb7a40f..039b929f7 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -171,7 +171,7 @@ namespace AST void meminfo(int &mem_width, int &mem_size, int &addr_bits); // create a human-readable text representation of the AST (for debugging) - void dumpAst(FILE *f, std::string indent, AstNode *other = NULL); + void dumpAst(FILE *f, std::string indent); void dumpVlog(FILE *f, std::string indent); // used by genRTLIL() for detecting expression width and sign @@ -195,7 +195,7 @@ namespace AST }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code - void process(RTLIL::Design *design, AstNode *ast, bool dump_ast = false, bool dump_ast_diff = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false); + void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false); // parametric modules are supported directly by the AST library // therfore we need our own derivate of RTLIL::Module with overloaded virtual functions @@ -224,7 +224,7 @@ namespace AST namespace AST_INTERNAL { // internal state variables - extern bool flag_dump_ast, flag_dump_ast_diff, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt; + extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt; extern AST::AstNode *current_ast, *current_ast_mod; extern std::map<std::string, AST::AstNode*> current_scope; extern RTLIL::SigSpec *genRTLIL_subst_from, *genRTLIL_subst_to, ignoreThisSignalsInInitial; |