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authorJim Lawson <ucbjrl@berkeley.edu>2018-08-22 08:42:34 -0700
committerGitHub <noreply@github.com>2018-08-22 08:42:34 -0700
commit2c0601eb6f2c5ed0d376ed880efda48a2aeeb9ef (patch)
tree02b9412c9249cce3714972c8385d66f8093bfc17 /frontends/ast/ast.h
parent8b92ddb9d2635c30636b17ff3d24bc09a44b8551 (diff)
parent408077769ff022f78f10ec1ffb60926361f8dc9f (diff)
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Merge pull request #1 from YosysHQ/master
merge with YosysHQ master
Diffstat (limited to 'frontends/ast/ast.h')
-rw-r--r--frontends/ast/ast.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 756629aca..d94199643 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -1,4 +1,4 @@
-/*
+/* -*- c++ -*-
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
@@ -168,7 +168,7 @@ namespace AST
// node content - most of it is unused in most node types
std::string str;
std::vector<RTLIL::State> bits;
- bool is_input, is_output, is_reg, is_signed, is_string, range_valid, range_swapped;
+ bool is_input, is_output, is_reg, is_logic, is_signed, is_string, range_valid, range_swapped, was_checked;
int port_id, range_left, range_right;
uint32_t integer;
double realvalue;
@@ -282,9 +282,9 @@ namespace AST
struct AstModule : RTLIL::Module {
AstNode *ast;
bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
- virtual ~AstModule();
- virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail);
- virtual RTLIL::Module *clone() const;
+ ~AstModule() YS_OVERRIDE;
+ RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE;
+ RTLIL::Module *clone() const YS_OVERRIDE;
};
// this must be set by the language frontend before parsing the sources