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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-09 14:31:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-09 14:31:57 +0200 |
| commit | 00a6c1d9a57da0e0b0fef07b2d618847ed93a9fd (patch) | |
| tree | 149e564703234381d2c8f03e6698bede1735fd53 /frontends/ast/ast.h | |
| parent | e8da3ea7b647f2c1eeba8a84590df7b05ca4e046 (diff) | |
| download | yosys-00a6c1d9a57da0e0b0fef07b2d618847ed93a9fd.tar.gz yosys-00a6c1d9a57da0e0b0fef07b2d618847ed93a9fd.tar.bz2 yosys-00a6c1d9a57da0e0b0fef07b2d618847ed93a9fd.zip | |
Major redesign of expr width/sign detecion (verilog/ast frontend)
Diffstat (limited to 'frontends/ast/ast.h')
| -rw-r--r-- | frontends/ast/ast.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 12e9a71bc..99760e09c 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -174,10 +174,14 @@ namespace AST void dumpAst(FILE *f, std::string indent, AstNode *other = NULL); void dumpVlog(FILE *f, std::string indent); + // used by genRTLIL() for detecting expression width and sign + void detectSignWidthWorker(int &width_hint, bool &sign_hint); + void detectSignWidth(int &width_hint, bool &sign_hint); + // create RTLIL code for this AST node // for expressions the resulting signal vector is returned // all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module - RTLIL::SigSpec genRTLIL(int width_hint = -1); + RTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false); RTLIL::SigSpec genWidthRTLIL(int width, RTLIL::SigSpec *subst_from = NULL, RTLIL::SigSpec *subst_to = NULL); // compare AST nodes |