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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-15 13:35:41 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-15 13:35:41 +0200 |
| commit | 3d27c1cc80da1c631bf5eb9c0b6b27e74ca73873 (patch) | |
| tree | 571f3835d5202c2540eed44b342ff187a65ce13b /frontends/ast/ast.cc | |
| parent | d71529baa1deb224ab520b2431b2c1a176170054 (diff) | |
| parent | 73d426bc879087ca522ca595a8ba921b647fae27 (diff) | |
| download | yosys-3d27c1cc80da1c631bf5eb9c0b6b27e74ca73873.tar.gz yosys-3d27c1cc80da1c631bf5eb9c0b6b27e74ca73873.tar.bz2 yosys-3d27c1cc80da1c631bf5eb9c0b6b27e74ca73873.zip | |
Merge pull request #513 from udif/pr_reg_wire_error
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
Diffstat (limited to 'frontends/ast/ast.cc')
| -rw-r--r-- | frontends/ast/ast.cc | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 54ce6a05d..7c72a50d9 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -191,8 +191,10 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch is_input = false; is_output = false; is_reg = false; + is_logic = false; is_signed = false; is_string = false; + was_checked = false; range_valid = false; range_swapped = false; port_id = 0; @@ -285,7 +287,9 @@ void AstNode::dumpAst(FILE *f, std::string indent) const fprintf(f, " input"); if (is_output) fprintf(f, " output"); - if (is_reg) + if (is_logic) + fprintf(f, " logic"); + if (is_reg) // this is an AST dump, not Verilog - if we see "logic reg" that's fine. fprintf(f, " reg"); if (is_signed) fprintf(f, " signed"); @@ -652,6 +656,8 @@ bool AstNode::operator==(const AstNode &other) const return false; if (is_output != other.is_output) return false; + if (is_logic != other.is_logic) + return false; if (is_reg != other.is_reg) return false; if (is_signed != other.is_signed) |