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| author | Stefan Biereigel <stefan.biereigel@cern.ch> | 2019-05-23 10:16:41 +0200 |
|---|---|---|
| committer | Stefan Biereigel <stefan.biereigel@cern.ch> | 2019-05-23 13:57:27 +0200 |
| commit | 075a48d3fa69324d5b2700779a686fa46a69adb2 (patch) | |
| tree | 879f47ad58c6f9f6a54a30c0e3de99c349b1fd9a /frontends/ast/ast.cc | |
| parent | 9df04d7e7520884bfc40004bb131cfdb474061c7 (diff) | |
| download | yosys-075a48d3fa69324d5b2700779a686fa46a69adb2.tar.gz yosys-075a48d3fa69324d5b2700779a686fa46a69adb2.tar.bz2 yosys-075a48d3fa69324d5b2700779a686fa46a69adb2.zip | |
implementation for assignments working
Diffstat (limited to 'frontends/ast/ast.cc')
| -rw-r--r-- | frontends/ast/ast.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 5623541b2..9c360efb6 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -51,6 +51,7 @@ namespace AST_INTERNAL { std::map<std::string, AstNode*> current_scope; const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL; RTLIL::SigSpec ignoreThisSignalsInInitial; + std::map<RTLIL::SigSpec, RTLIL::Cell*> wire_logic_map; AstNode *current_always, *current_top_block, *current_block, *current_block_child; AstModule *current_module; bool current_always_clocked; @@ -940,6 +941,8 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast log("--- END OF AST DUMP ---\n"); } + wire_logic_map = std::map<RTLIL::SigSpec, RTLIL::Cell*>(); + if (!defer) { bool blackbox_module = flag_lib; |