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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-08 13:17:53 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-08 13:17:53 -0800 |
| commit | 8886fa5506b227229398e5ac884203e799bce22c (patch) | |
| tree | 026088414bb75c4e3e85e8fe5352833ed3b2344e /frontends/aiger | |
| parent | afc3c4b6139db528b58062f544fb0b098ab212b0 (diff) | |
| download | yosys-8886fa5506b227229398e5ac884203e799bce22c.tar.gz yosys-8886fa5506b227229398e5ac884203e799bce22c.tar.bz2 yosys-8886fa5506b227229398e5ac884203e799bce22c.zip | |
addDff -> addDffGate as per @daveshah1
Diffstat (limited to 'frontends/aiger')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 154581179..c45de8531 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -176,7 +176,7 @@ void AigerReader::parse_aiger_ascii() RTLIL::Wire *q_wire = createWireIfNotExists(module, l1); RTLIL::Wire *d_wire = createWireIfNotExists(module, l2); - module->addDff(NEW_ID, clk_wire, d_wire, q_wire); + module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire); // Reset logic is optional in AIGER 1.9 if (f.peek() == ' ') { |