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authorEddie Hung <eddie@fpgeh.com>2020-01-15 14:31:32 -0800
committerEddie Hung <eddie@fpgeh.com>2020-01-15 14:31:32 -0800
commit05c8858a907f0f188f1687ede260c2e1a97efe38 (patch)
treecc3965771560946a731408dc7add14d6eff62038 /frontends/aiger
parentffd6f54f92a7ba3856b5f168b7db97eb8ed87caa (diff)
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read_aiger: $lut prefix in front
Diffstat (limited to 'frontends/aiger')
-rw-r--r--frontends/aiger/aigerparse.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index f6b2a639d..a4b1e6fec 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -1001,9 +1001,9 @@ void AigerReader::post_process()
if (cell->type != "$lut") continue;
auto y_port = cell->getPort("\\Y").as_bit();
if (y_port.wire->width == 1)
- module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str()));
+ module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str()));
else
- module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset));
+ module->rename(cell, stringf("$lut%s[%d]", y_port.wire->name.c_str(), y_port.offset));
}
}