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author | Aman Goel <amangoel@umich.edu> | 2019-09-27 12:30:27 -0400 |
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committer | GitHub <noreply@github.com> | 2019-09-27 12:30:27 -0400 |
commit | cb0dc6e68b9432edc9c30c153954be53c8576911 (patch) | |
tree | c137f970f949117d04632158d73bfe1f9c146e6f /frontends/aiger/aigerparse.h | |
parent | 4d343fc1cdafe469484846051680ca0b1f948549 (diff) | |
parent | 4b15cf5f76e2226bbce1a73d1e0ff54fbf093fe8 (diff) | |
download | yosys-cb0dc6e68b9432edc9c30c153954be53c8576911.tar.gz yosys-cb0dc6e68b9432edc9c30c153954be53c8576911.tar.bz2 yosys-cb0dc6e68b9432edc9c30c153954be53c8576911.zip |
Merge pull request #7 from YosysHQ/master
Syncing with official repo
Diffstat (limited to 'frontends/aiger/aigerparse.h')
-rw-r--r-- | frontends/aiger/aigerparse.h | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h new file mode 100644 index 000000000..583c9d0f9 --- /dev/null +++ b/frontends/aiger/aigerparse.h @@ -0,0 +1,58 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * 2019 Eddie Hung <eddie@fpgeh.com> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef ABC_AIGERPARSE +#define ABC_AIGERPARSE + +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +struct AigerReader +{ + RTLIL::Design *design; + std::istream &f; + RTLIL::IdString clk_name; + RTLIL::Module *module; + std::string map_filename; + bool wideports; + + unsigned M, I, L, O, A; + unsigned B, C, J, F; // Optional in AIGER 1.9 + unsigned line_count; + uint32_t piNum, flopNum; + + std::vector<RTLIL::Wire*> inputs; + std::vector<RTLIL::Wire*> latches; + std::vector<RTLIL::Wire*> outputs; + std::vector<RTLIL::Wire*> bad_properties; + std::vector<RTLIL::Cell*> boxes; + + AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports); + void parse_aiger(); + void parse_xaiger(const dict<int,IdString> &box_lookup); + void parse_aiger_ascii(); + void parse_aiger_binary(); + void post_process(); +}; + +YOSYS_NAMESPACE_END + +#endif |