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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-09 14:31:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 10:33:56 -0700 |
| commit | 53fc3ed64563045949bcd52a03d2af586605d523 (patch) | |
| tree | 0e34bbff272bc6a23e3fcaa335a6b9e63e3461aa /frontends/aiger/aigerparse.h | |
| parent | ffa52738fba1264ef2eb37d5333babfa0758fe48 (diff) | |
| download | yosys-53fc3ed64563045949bcd52a03d2af586605d523.tar.gz yosys-53fc3ed64563045949bcd52a03d2af586605d523.tar.bz2 yosys-53fc3ed64563045949bcd52a03d2af586605d523.zip | |
aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created
according to mergeability class, and init state as cell attr
Diffstat (limited to 'frontends/aiger/aigerparse.h')
| -rw-r--r-- | frontends/aiger/aigerparse.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h index 46ac81212..251a24977 100644 --- a/frontends/aiger/aigerparse.h +++ b/frontends/aiger/aigerparse.h @@ -45,7 +45,7 @@ struct AigerReader std::vector<RTLIL::Wire*> outputs; std::vector<RTLIL::Wire*> bad_properties; std::vector<RTLIL::Cell*> boxes; - std::vector<int> mergeability; + std::vector<int> mergeability, initial_state; AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports); void parse_aiger(); |