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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 09:10:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-15 09:10:01 -0700 |
| commit | 7a3c403ba0e411c990be59da44e1decb6aafc8f8 (patch) | |
| tree | 06c9038f690302530ea66514a84d808a8cf53bb5 /frontends/aiger/aigerparse.cc | |
| parent | 295bb23ae06d36acc8ced4825ece6003470cd357 (diff) | |
| download | yosys-7a3c403ba0e411c990be59da44e1decb6aafc8f8.tar.gz yosys-7a3c403ba0e411c990be59da44e1decb6aafc8f8.tar.bz2 yosys-7a3c403ba0e411c990be59da44e1decb6aafc8f8.zip | |
Missing close bracket
Diffstat (limited to 'frontends/aiger/aigerparse.cc')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 281e1cc9d..d0d2ffdba 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -1025,7 +1025,7 @@ struct AigerFrontend : public Frontend { log(" Name of module to be created (default: <filename>)\n"); log("\n"); log(" -clk_name <wire_name>\n"); - log(" If specified, AIGER latches to be transformed into $_DFF_P_ cells\n" + log(" If specified, AIGER latches to be transformed into $_DFF_P_ cells\n"); log(" clocked by wire of this name. Otherwise, $_FF_ cells will be used.\n"); log("\n"); log(" -map <filename>\n"); |