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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 13:35:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 13:35:39 -0700 |
| commit | 6b156beda16cce69e7318a3a2fdbc3ad547370c6 (patch) | |
| tree | 0a3de2600b909c9b141193c3c9e075d912ff5fed /frontends/aiger/aigerparse.cc | |
| parent | 49301b733eede41f2a4165440eee68c1a71f36e6 (diff) | |
| download | yosys-6b156beda16cce69e7318a3a2fdbc3ad547370c6.tar.gz yosys-6b156beda16cce69e7318a3a2fdbc3ad547370c6.tar.bz2 yosys-6b156beda16cce69e7318a3a2fdbc3ad547370c6.zip | |
Remove unused variable
Diffstat (limited to 'frontends/aiger/aigerparse.cc')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 534cc0daa..ac9e31f70 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -901,11 +901,6 @@ void AigerReader::post_process() RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable)); if (cell) { // ABC could have optimised this box away module->rename(cell, escaped_s); - #ifndef NDEBUG - RTLIL::Module* box_module = design->module(cell->type); - log_assert(box_module); - #endif - for (const auto &i : cell->connections()) { RTLIL::IdString port_name = i.first; RTLIL::SigSpec rhs = i.second; |