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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-28 21:35:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-28 21:35:33 +0200 |
| commit | eae390ae17839bf0273b32149f46a2560a23d934 (patch) | |
| tree | 218b3327ef63938a762859386f23215cef83c4d3 /examples | |
| parent | 66582964bc11aadf3d0783a346706d801451a13f (diff) | |
| download | yosys-eae390ae17839bf0273b32149f46a2560a23d934.tar.gz yosys-eae390ae17839bf0273b32149f46a2560a23d934.tar.bz2 yosys-eae390ae17839bf0273b32149f46a2560a23d934.zip | |
Removed $predict again
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/smtbmc/demo1.v | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/examples/smtbmc/demo1.v b/examples/smtbmc/demo1.v index 323e6c29c..d9be41513 100644 --- a/examples/smtbmc/demo1.v +++ b/examples/smtbmc/demo1.v @@ -10,7 +10,6 @@ module demo1(input clk, input addtwo, output iseven); `ifdef FORMAL assert property (cnt != 15); initial assume (!cnt[3] && !cnt[0]); - // initial predict ((iseven && addtwo) || cnt == 9); `endif endmodule |