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authorSergey <37293587+SergeyDegtyar@users.noreply.github.com>2019-08-29 21:07:34 +0300
committerGitHub <noreply@github.com>2019-08-29 21:07:34 +0300
commitd360693040dda29aba4ef2583e522c6ab88a4961 (patch)
tree3de073925c8e3a4a613303ea807aeef12949a3d7 /examples
parentd588c6898fb7cfebe52a71a48d6fb21d1623e61b (diff)
parentb8a9f73089234ed699a4057b50fd739a90abea43 (diff)
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Merge pull request #3 from YosysHQ/Sergey/tests_ice40
Merge my changes to tests_ice40 branch
Diffstat (limited to 'examples')
-rw-r--r--examples/mimas2/run_yosys.ys3
1 files changed, 1 insertions, 2 deletions
diff --git a/examples/mimas2/run_yosys.ys b/examples/mimas2/run_yosys.ys
index b3204b1ca..b48877811 100644
--- a/examples/mimas2/run_yosys.ys
+++ b/examples/mimas2/run_yosys.ys
@@ -1,4 +1,3 @@
read_verilog example.v
-synth_xilinx -top example -family xc6s
-iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I
+synth_xilinx -top example -family xc6s -ise
write_edif -pvector bra example.edif