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| author | Udi Finkelstein <github@udifink.com> | 2018-09-18 01:27:01 +0300 |
|---|---|---|
| committer | Udi Finkelstein <github@udifink.com> | 2018-09-18 01:27:01 +0300 |
| commit | c693f595c53e2e40840ff40b5b5ba06767582d23 (patch) | |
| tree | de5e3f353f3222abca7186996e88cd9d635a964b /examples | |
| parent | f6fe73b31f6e6d8966ad4ddae860b4d79133cce2 (diff) | |
| parent | 592a82c0ad8beb6de023aa2a131aab6472f949e8 (diff) | |
| download | yosys-c693f595c53e2e40840ff40b5b5ba06767582d23.tar.gz yosys-c693f595c53e2e40840ff40b5b5ba06767582d23.tar.bz2 yosys-c693f595c53e2e40840ff40b5b5ba06767582d23.zip | |
Merge branch 'master' into pr_reg_wire_error
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/basys3/example.xdc | 3 | ||||
| -rw-r--r-- | examples/basys3/run_prog.tcl | 1 | ||||
| -rw-r--r-- | examples/cmos/counter.ys | 10 | ||||
| -rw-r--r-- | examples/cxx-api/evaldemo.cc | 2 |
4 files changed, 10 insertions, 6 deletions
diff --git a/examples/basys3/example.xdc b/examples/basys3/example.xdc index c1fd0e925..8cdaa1996 100644 --- a/examples/basys3/example.xdc +++ b/examples/basys3/example.xdc @@ -19,3 +19,6 @@ set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1 } [get_ports {LD[15]}] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + diff --git a/examples/basys3/run_prog.tcl b/examples/basys3/run_prog.tcl index d711af840..b078ad511 100644 --- a/examples/basys3/run_prog.tcl +++ b/examples/basys3/run_prog.tcl @@ -1,3 +1,4 @@ +open_hw connect_hw_server open_hw_target [lindex [get_hw_targets] 0] set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0] diff --git a/examples/cmos/counter.ys b/examples/cmos/counter.ys index a784f3465..d0b093667 100644 --- a/examples/cmos/counter.ys +++ b/examples/cmos/counter.ys @@ -1,11 +1,12 @@ - read_verilog counter.v read_verilog -lib cmos_cells.v -proc;; memory;; techmap;; - +synth dfflibmap -liberty cmos_cells.lib -abc -liberty cmos_cells.lib;; +abc -liberty cmos_cells.lib +opt_clean + +stat -liberty cmos_cells.lib # http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib # dfflibmap -liberty osu025_stdcells.lib @@ -13,4 +14,3 @@ abc -liberty cmos_cells.lib;; write_verilog synth.v write_spice synth.sp - diff --git a/examples/cxx-api/evaldemo.cc b/examples/cxx-api/evaldemo.cc index e5cc8d8e7..34373487d 100644 --- a/examples/cxx-api/evaldemo.cc +++ b/examples/cxx-api/evaldemo.cc @@ -22,7 +22,7 @@ struct EvalDemoPass : public Pass { EvalDemoPass() : Pass("evaldemo") { } - virtual void execute(vector<string>, Design *design) + void execute(vector<string>, Design *design) YS_OVERRIDE { Module *module = design->top_module(); |