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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-24 23:18:29 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-24 23:18:29 +0200 |
| commit | ad56ad44c3bdd3d075a32879785a04e3e30491eb (patch) | |
| tree | cf6fed0b983356ef46dbbdcc6f92e13ac08801ce /examples/smtbmc | |
| parent | ee3e7a0e45e764c2655391b0e444e4379c97fe3c (diff) | |
| download | yosys-ad56ad44c3bdd3d075a32879785a04e3e30491eb.tar.gz yosys-ad56ad44c3bdd3d075a32879785a04e3e30491eb.tar.bz2 yosys-ad56ad44c3bdd3d075a32879785a04e3e30491eb.zip | |
More yosys-smtbmc smtc features
Diffstat (limited to 'examples/smtbmc')
| -rw-r--r-- | examples/smtbmc/.gitignore | 5 | ||||
| -rw-r--r-- | examples/smtbmc/Makefile | 15 | ||||
| -rw-r--r-- | examples/smtbmc/demo3.smtc | 5 | ||||
| -rw-r--r-- | examples/smtbmc/demo3.v | 18 |
4 files changed, 38 insertions, 5 deletions
diff --git a/examples/smtbmc/.gitignore b/examples/smtbmc/.gitignore index 1c9afd5ba..bf83e0d44 100644 --- a/examples/smtbmc/.gitignore +++ b/examples/smtbmc/.gitignore @@ -1,9 +1,12 @@ demo1.smt2 demo1.yslog demo2.smt2 +demo2.smtc demo2.vcd demo2.yslog demo2_tb -demo2_tb.smtc demo2_tb.v demo2_tb.vcd +demo3.smt2 +demo3.vcd +demo3.yslog diff --git a/examples/smtbmc/Makefile b/examples/smtbmc/Makefile index a266567e4..b3feb07c7 100644 --- a/examples/smtbmc/Makefile +++ b/examples/smtbmc/Makefile @@ -1,24 +1,31 @@ -all: demo1 demo2 +all: demo1 demo2 demo3 demo1: demo1.smt2 yosys-smtbmc --dump-vcd demo1.vcd demo1.smt2 yosys-smtbmc -i --dump-vcd demo1.vcd demo1.smt2 demo2: demo2.smt2 - yosys-smtbmc -g --dump-vcd demo2.vcd --dump-vlogtb demo2_tb.v --dump-smtc demo2_tb.smtc demo2.smt2 + yosys-smtbmc -g --dump-vcd demo2.vcd --dump-smtc demo2.smtc --dump-vlogtb demo2_tb.v demo2.smt2 iverilog -g2012 -o demo2_tb demo2_tb.v demo2.v vvp demo2_tb +vcd=demo2_tb.vcd +demo3: demo3.smt2 + yosys-smtbmc --dump-vcd demo3.vcd --smtc demo3.smtc demo3.smt2 + demo1.smt2: demo1.v yosys -ql demo1.yslog -p 'read_verilog -formal demo1.v; prep -top demo1 -nordff; write_smt2 -wires -mem -bv demo1.smt2' demo2.smt2: demo2.v yosys -ql demo2.yslog -p 'read_verilog -formal demo2.v; prep -top demo2 -nordff; write_smt2 -wires -mem -bv demo2.smt2' +demo3.smt2: demo3.v + yosys -ql demo3.yslog -p 'read_verilog -formal demo3.v; prep -top demo3 -nordff; write_smt2 -wires -mem -bv demo3.smt2' + clean: rm -f demo1.yslog demo1.smt2 demo1.vcd - rm -f demo2.yslog demo2.smt2 demo2.vcd demo2_tb.v demo2_tb demo2_tb.vcd demo2_tb.smtc + rm -f demo2.yslog demo2.smt2 demo2.vcd demo2.smtc demo2_tb.v demo2_tb demo2_tb.vcd + rm -f demo3.yslog demo3.smt2 demo3.vcd -.PHONY: demo1 clean +.PHONY: demo1 demo2 demo3 clean diff --git a/examples/smtbmc/demo3.smtc b/examples/smtbmc/demo3.smtc new file mode 100644 index 000000000..f5e017cf0 --- /dev/null +++ b/examples/smtbmc/demo3.smtc @@ -0,0 +1,5 @@ +initial +assume [rst] + +always -1 +assert (= [-1:mem] [mem]) diff --git a/examples/smtbmc/demo3.v b/examples/smtbmc/demo3.v new file mode 100644 index 000000000..13b3a1970 --- /dev/null +++ b/examples/smtbmc/demo3.v @@ -0,0 +1,18 @@ +// Whatever the initial content of this memory is at reset, it will never change +// see demo3.smtc for assumptions and assertions + +module demo3(input clk, rst, input [15:0] addr, output reg [31:0] data); + reg [31:0] mem [0:2**16-1]; + reg [15:0] addr_q; + + always @(posedge clk) begin + if (rst) begin + data <= mem[0] ^ 123456789; + addr_q <= 0; + end else begin + mem[addr_q] <= data ^ 123456789; + data <= mem[addr] ^ 123456789; + addr_q <= addr; + end + end +endmodule |