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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-25 10:49:26 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-25 10:49:26 -0700 |
| commit | a02d1720a766ae1b993a9884e840f37b3d785b8f (patch) | |
| tree | d11cde6c9cb30afc8a54d49834d79facf94bb5a7 /examples/mimas2/example.v | |
| parent | c5e31ac9c3c49f38ddcb6e613ef4a092d69f71a2 (diff) | |
| parent | eb663c75794d1249247ba88bf0bee835c98a8a85 (diff) | |
| download | yosys-a02d1720a766ae1b993a9884e840f37b3d785b8f.tar.gz yosys-a02d1720a766ae1b993a9884e840f37b3d785b8f.tar.bz2 yosys-a02d1720a766ae1b993a9884e840f37b3d785b8f.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'examples/mimas2/example.v')
| -rw-r--r-- | examples/mimas2/example.v | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/examples/mimas2/example.v b/examples/mimas2/example.v new file mode 100644 index 000000000..2a9117393 --- /dev/null +++ b/examples/mimas2/example.v @@ -0,0 +1,14 @@ +module example( + input wire CLK, + output wire [7:0] LED +); + +reg [27:0] ctr; +initial ctr = 0; + +always @(posedge CLK) + ctr <= ctr + 1; + +assign LED = ctr[27:20]; + +endmodule |