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| author | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-07-24 18:41:39 +0200 |
|---|---|---|
| committer | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-07-24 18:59:03 +0200 |
| commit | 173c97589471b5f4312acac4e396a250ee7158c1 (patch) | |
| tree | 0303e68642bb955029a71788beb1efabc7437c7e /examples/mimas2/example.v | |
| parent | a66f17b6a78af8f6989235f0c72d5548b0560a58 (diff) | |
| download | yosys-173c97589471b5f4312acac4e396a250ee7158c1.tar.gz yosys-173c97589471b5f4312acac4e396a250ee7158c1.tar.bz2 yosys-173c97589471b5f4312acac4e396a250ee7158c1.zip | |
Add a simple example for Spartan 6
Diffstat (limited to 'examples/mimas2/example.v')
| -rw-r--r-- | examples/mimas2/example.v | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/examples/mimas2/example.v b/examples/mimas2/example.v new file mode 100644 index 000000000..2a9117393 --- /dev/null +++ b/examples/mimas2/example.v @@ -0,0 +1,14 @@ +module example( + input wire CLK, + output wire [7:0] LED +); + +reg [27:0] ctr; +initial ctr = 0; + +always @(posedge CLK) + ctr <= ctr + 1; + +assign LED = ctr[27:20]; + +endmodule |